The present invention relates to a method of manufacturing CMOS EPROM memory cells. As is known, the manufacture of EPROM memories produced with CMOS technology entails carrying out various process steps, generally comprising the production, in a substrate having a first type of conductivity, of zones having a second type of conductivity, the growth of field oxide regions between the individual transistors, the implantation of atoms in the regions in which the memory cells are to be provided, the formation of a first layer of oxide on the entire surface of the semiconductor body, the adjustment of the threshold of the N- and P-channel devices, the deposition of a first layer of polycrystalline silicon at least on the regions in which the memory cells are to be provided, the deposition of a dielectric layer over the first layer of polycrystalline silicon, the deposition of a third layer of polycrystalline silicon on the entire surface, the formation of a layer of oxide on the second polysilicon layer, and the masking for the definition of the gate regions of the memory cells and CMOS transistors, obtaining the structure illustrated by way of example in FIG. 14. According to the known art, the removal of the layer of surface oxide, of polysilicon and of uncovered oxide is effected for the formation of the gate regions of the transistors. Then a further self-aligned polysilicon masking step is performed for the removal of the portions of the first layer of polysilicon around the floating gate of the memory cells, then, by means of two further masks, the ion implantations for the formation of the source and drain regions of the transistors are performed. Lastly, a final oxidation is effected, followed by the realization of the contacts and metallizations and the deposition of a passivation layer as well as the formation of the contact pads.
Consequently, the method requires a certain number of masking steps which, as known, have a relatively high cost. The need is therefore felt to modify the manufacturing method so as to reduce the overall number of required steps, in particular the number of masking steps and of masks employed.